1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two parts of different thickness suitable for diminishing irregular thickness of the field oxide layer.
2. Description of the Related Art
Non-volatile memory devices such as flash EEPROMs (Electrically Erasable Programmable Read Only Memory) and flash memory cards are recently finding many uses. One very important issue associated with the use of non-volatile semiconductor memory devices, such as in mass storage media, is a high cost per bit of storage. In addition, the memory chip should have low power consumption to be used for portable instruments. Recently, there has been much effort to develop the multi-bit per cell memory. In a multi-bit per cell (hereinafter referred to as multi-bit cell) more than one bit is stored in a single cell to enhance the storage capacity, compared to the cells of the conventional nonvolatile memory devices, in which each cell corresponds to a single bit of data.
The multi-bit cell requires three or more threshold voltage levels to be programmed in each memory cell. For example, in order to store two bits in each cell, the number of the threshold voltage levels should be 22=4. In this case, the four levels are made to respectively correspond to the logic states 00, 01, 10, and 11. In such multi-level programming, each threshold voltage level has a statistical distribution of about 0.5V. Accordingly, as each threshold level is precisely adjusted to reduce its distribution range, the number of the threshold levels is increased, and so is the number of data bits stored in each cell. One of the methods for reducing such threshold level distribution is to alternately repeat the steps of programming and verifying. That is, while a series of programming voltage pulses is applied to the non-volatile memory cell to be programmed with desired threshold levels, reading is performed between the series of voltage pulses in order to verify that the cell has reached the desired levels. If the verification shows that each level has been reached, the programming is stopped. However, such a method cannot readily reduce the error distributions of the threshold levels due to the limited pulse widths of the programming voltage. Moreover, the algorithm for repeatedly alternating programming and verifying requires an additional circuit which increases the size of the peripheral circuit region. Further, the alternate repetition of programming and verifying increases the programming time. The cell size and cell array structure generally affect the effective cell size of the memory cell determining the integration scale of a non-volatile memory device such as EEPROM or flash EEPROM.
FIGS. 1A and 1B illustrate respectively both circuit diagram and cross sectional view of the fundamental cell structure of a non-volatile memory device composed of deposited layers. Referring to FIG. 1A, the circuit diagram of the memory cell shows a control gate 5, floating gate 3, source 6a, channel region 7, and drain 6b. When a program voltage is applied to the control gate 5 and drain 6b, a current flows between the drain 6b and source 6a. If the amount of the current flowing is equal to or less than that of the reference current, there is generated the programming completion signal. Referring to FIG. 1B, deposited over a p-type semiconductor substrate 1 is a floating gate 3 with a tunnel oxide layer 2 interposed between them. The control gate 5 is deposited over the floating gate 3 with a dielectric layer 4 between them. The n-type source and drain regions 6a and 6b are respectively formed at both sides of the floating gate 3 in the p-type semiconductor substrate 1.
Although the effective cell size of such a non-volatile memory device simply deposited is small, the coupling constant of the control gate 5 has a small value, being additionally smaller when reducing the effective cell size. In order to resolve this, an ONO (oxide-nitride-oxide) layer is used for the dielectric layer 4 between the floating gate 3 and control gate 5. This ONO layer, together with a required additional annealing process, complicates the fabrication process.
The non-volatile memory device comprises the cell transistors for storing information, and the auxiliary transistors both for applying the external voltage and for interfacing with peripheral circuits. Accordingly, the tunnel insulating layer 2 below the floating gate 3 is different for a low voltage transistor and a high voltage transistor.
A conventional method of fabricating a non-volatile memory device having a tunnel insulating layer consisting of two portions of different thickness will now be described in connection with FIGS. 2A to 2D. Referring FIG. 2A, sequentially deposited over a semiconductor substrate 21 are a tunnel insulating layer 22 consisting of two portions of different thickness. A conductive layer 23 is formed over the tunnel insulating layer, and a first insulating layer 24 is formed over the conductive layer 23. Then, a photoresist layer is deposited over the first insulating layer 24. The photoresist layer is exposed and developed to generate a photoresist patter PR1. In this case, the first insulating layer 24 may be a nitride layer.
Referring to FIG. 2B, the photoresist pattern PR1 is used as a mask to sequentially selectively etch the first insulating layer 24, conductive layer 23, tunnel insulating layer 22, and semiconductor substrate 21 through self-alignment to form trenches. Then, a second insulating layer 25 is deposited over the substrate including the trenches. In this case, the second insulating layer 25 may be achieved by using HDP (High Density Plasma). Subsequently, CMP (Chemical Mechanical Polishing) is performed to flatten the upper surface of the resultant structure as shown in FIG. 2C. The HDP layer 25 is selectively etched through photolithography then subjected to CMP to form element isolation regions with HDP layer 25 contained only in the trenches.
When using such a structure in the formation of a high voltage transistor and a low voltage transistor, the step between the high voltage transistor and the element isolation region forms a dielectric difference with the step between the low voltage transistor and the element isolation region because of the thickness difference between the high and low voltage portions of the tunnel insulating layers. Such a thickness difference of the tunnel-insulating layer adversely affects the flattening of the HDP layer after CMP. Then, removing the first insulating layer 24 from the floating gate 23 by means of a wet etching process as shown in FIG. 2D, a dielectric layer (not shown) is deposited over the floating gate 23, over which the control gate is formed. In this case, the second insulating layer 25 produces a negative slope in the element isolation region, so that the subsequent etching process of the control gate cannot completely remove the conductive layer, thus producing stringers.
Therefore, the conventional non-volatile memory device having a tunnel-insulating layer consisting of two or more portions of different thickness inherently suffers from several drawbacks. For example, when flattening the element isolation regions through the CMP process, the step difference between the floating gate and element isolation regions may cause failure of the subsequent contact opening, short circuit between the gates due to the fine residue remaining in the gates, or humped transistor. In addition, if the step between the floating gate and element isolation region is high, the thickness of the nitride layer serving as the stopping layer is increased so as to reduce the contact etching margin, which causes failure of the contact opening. Moreover, the property of the insulating layer, e.g., HDP layer, used for the element isolation causes the negative slope in the element isolation regions, so that the subsequent etching process cannot completely etch the control gate. In order to reduce the negative slope, an additional wet etching process is used to diminish the insulating layer in the element isolation regions, which complicates the fabrication process. Alternatively, if the step between the floating gate and the element isolation region is small, the insulating layer in the element isolation region contacts the tunnel-insulating layer causing a humped transistor.
It is an object of the present invention to provide a method of fabricating a non-volatile memory device having a tunnel-insulating layer consisting of more than two parts of different thickness suitable for reducing the step between the floating gate and the insulating layer of the element isolation region.
The invention is directed to a method of fabricating a non-volatile memory device, which has a tunnel insulating layer consisting of two or more portions of different thickness, cell transistors, and auxiliary transistors for applying external voltage and for interfacing with peripheral circuits. In accordance with the method, the tunnel insulating layer, a conductive layer, and a first insulating layer are sequentially deposited over a semiconductor substrate. The resultant structure is selectively etched to a given depth to form trenches. A second insulating layer is deposited over the structure including the trenches. The second insulating layer is selectively removed so as to form element isolation regions consisting of the trenches filled with the second insulating layer. The first insulating layer is removed, and the second insulating layer is selectively removed by a CMP process until the conductive layer is exposed, the conductive layer being used as the stopping layer for the CMP process.
In one embodiment, the conductive layer serves as a floating gate in a transistor device formed as part of a memory cell in the memory device.
The conductive layer can have a thickness of between 50 and 1000 xc3x85. The first insulating layer can be formed of a material selected from the group consisting of SiN, BN and CN. The first insulating layer can have a thickness between 100 and 1000 xc3x85. The second insulating layer can be formed of a material selected from the group consisting of HDP, BPSG, SOG, Fox, USG, HOSP, and black diamond.
In one embodiment, selectively removing the second insulating layer by the CMP process employs a slurry with selectivity between said second insulating layer and the conductive layer equal to or greater than 1.
In one embodiment, selectively removing the second insulating layer includes subjecting the structure to photolithography to selectively etch the second insulating layer. The first and second insulating layers are flattened through a CMP process. Photolithography is performed to selectively remove the flattened first insulating layer. The second insulating layer is subjected to a CMP process to complete the element isolation regions. Selectively removing the flattened first insulating layer can be performed until the conductive layer is exposed.